Generally, integrated circuits may be formed from a plurality of semiconductor devices within a semiconductor die. As a starting point for this process, the semiconductor devices may be formed through a series of manufacturing steps including oxidation, implantation, deposition, photolithography, etching, annealing, chemical mechanical polishing. Once the semiconductor devices have been formed, a series of conductive and dielectric layers may be deposited or otherwise formed over the semiconductor devices in order to connect the individual devices to each other and also to provide a connection between the individual devices and external devices so that the integrated circuit may be integrated for use by a consumer.
However, as the integrated circuits and their associated semiconductor devices are scaled down to smaller and smaller sizes in the rush of miniaturization, issues have arisen at all levels of production. Such issues have included everything from achieving heightened precision in photolithographic masks to ensuring that an adequate coverage occurs in high-aspect ratio vias during a deposition process. At each level of miniaturization, these issues have needed to be addressed in order for the miniaturization to continue to meet the demands for consumer products.
One such issue that may occur as devices are scaled down beyond the twenty nanometer process node is defects that can occur in the semiconductor wafer onto which the various semiconductor devices, conductive, and dielectric layers are formed in order to make the integrated circuit. In particular, semiconductor wafers have a tendency to warp or deflect during high temperature processes. At smaller and smaller processing nodes, even minor warping or deflecting of the semiconductor wafer can lead to misalignments as the various manufacturing processes are performed on the semiconductor wafer.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.